In this type of multiprocessor system, each processor includes means for managing access to the main bus of the module to which it belongs by using a two-phase process. During a first phase, corresponding for example to one clock cycle, the whole set of bus access requests originating from all the processors in the module are handled by a priority arbitration logic in order to identify a winner in the assignments process. This "winner" then becomes the bus's next owner or "master". During a second phase, in other words when the bus of the module becomes available, the bus seizure circuit associated with the winning processor ensures exclusive access of the processor to the bus by sending a bus ownership signal.
In the case of multibus systems, the bus coupling modules are responsible for providing communication between the various processing modules on different buses which cooperate in a pairwise manner from one bus to the next. The communication is provided in order to establish two-way links using conventional access requests on the corresponding destination bus.
It will be noticed that transmission of data from one module to another can lead to passage through several successive buses in order to reach the destination processor.
In a known manner, interference in the signals travelling on the bus either as the result of a fault in the sending circuit or the receiving circuit on a board which is connected to the bus, or as a result of a short circuit in the back-plane, or for other reasons, can lead to either the allocation modules, or the bus seizure logic and bus management logic in the boards present on the bus becoming blocked. When such blocking takes place at the precise moment when a bus coupling module is in the process of communication with a remote module, the blocking situation can become propagated to other buses; in the worst case situation, complete blocking of the whole configuration can occur.
Procedures for unblocking-a multibus multiprocessor system exist already.
Among these procedures there are those known ones which consist of causing the system board to send a bus reset signal. The reset signal serves the purpose of acting on the connection registers of the processors in each module, and of the bus coupling modules, so as to forbid prevent each board from sending information over the bus. The boards, however, are not inhibited from receiving signals present on the bus.
However, the sending of a reset signal is poorly suited to multibus structures in which loops are present. In effect, in the case where at least three buses are linked together two-by-two, in a closed sequence or loop circuit, there is no way of stopping the sending of a reset signal covering the entire looped system. The reset signal is now in a self-maintaining situation as a result of the mechanisms which are specific to neutralization. This means that it is necessary to carry out the reset bus by bus, and not by means of a general reset.
On the other hand, the system board may, under certain circumstances, experience difficulties in gaining control of the bus either as the result of conflict with a bus coupling module board or as a result of loss of access priority to the bus.